View M36W416TG-ZAT_3164468.PDF datasheet online --- IC-ON-LINE

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1/62 preliminary data november 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. m36w416tg m36w416bg 16 mbit (1mb x16, boot block) flash memory and 4mbit (256kb x16) sram, multiple memory product features summary multiple memory product C 16 mbit (1mb x 16) boot block flash memory C 4 mbit (256kb x 16) sram supply voltage Cv ddf = v dds = 2.7v to 3.3v Cv ddqf = v dds = 2.7v to 3.3v Cv ppf = 12v for fast program (optional) access time: 70ns, 85ns low power consumption electronic signature C manufacturer code: 20h C top device code, m36w416tg: 88ceh C bottom device code, m36w416bg: 88cfh flash memory memory blocks C parameter blocks (top or bottom location) C main blocks programming time C 10s typical C double word programming option block locking C all blocks locked at power up C any combination of blocks can be locked Cwp f for block lock-down automatic stand-by mode program and erase suspend 100,000 program/erase cycles per block common flash interface C 64 bit security code security C 64 bit user programmable otp cells C 64 bit unique device identifier C one parameter block permanently lockable sram 4 mbit (256kb x 16) access time: 70ns low v dds data retention: 1.5v power down features using two chip enable inputs figure 1. packages fbga stacked lfbga66 (za) 12 x 8mm
m36w416tg, m36w416bg 2/62 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. lfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 address inputs (a0-a17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 address inputs (a18-a19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 data inputs/outputs (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash chip enable (ef). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash output enable (gf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash write enable (wf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash write protect (wpf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash reset (rpf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram chip enable (e1s, e2s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram write enable (ws). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram output enable (gs).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram upper byte enable (ubs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram lower byte enable (lbs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ddf and vdds supply voltages.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ddqf and v dds supply voltage (2.7v to 3.3v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ppf program supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ssf and v sss ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. main operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 table 5. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. stacked lfbga66-12x8mm, 8x8 ball array, 0.8mm pitch, bottom view package outline15 table 7. stacked lfbga66 - 12x8mm, 8x8 ball array, 0.8 mm pitch, package mechanical data . 15 figure 8. stacked lfbga66 daisy chain - package connections (top view through package) . . 16 figure 9. stacked lfbga66 daisy chain - pcb connections proposal (top view through package). 17
3/62 m36w416tg, m36w416bg part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 flash device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 flash summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. flash block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. flash security block and protection register memory map . . . . . . . . . . . . . . . . . . 20 flash bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 flash command interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 read memory array command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 read status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 read cfi query command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 double word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 clear status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. flash commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 table 11. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. read block lock signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. read protection register and lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. program, erase times and program/erase endurance cycles . . . . . . . . . . . . . . . . 26 flash block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 reading a blocks lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. block lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 16. protection status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
m36w416tg, m36w416bg 4/62 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 program status (bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 v pp status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 block protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 reserved (bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 17. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 12. flash read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 18. flash read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. flash write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . 32 table 19. flash write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . 33 figure 14. flash write ac waveforms, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . 34 table 20. flash write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . 35 figure 15. flash power-up and reset ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 21. flash power-up and reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 sram device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 sram summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 16. sram logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 sram operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 standby/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 17. sram read mode ac waveforms, address controlled with ubs = lbs = v il . . . 39 figure 18. sram read ac waveforms, gs controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19. sram standby ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 22. sram read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 20. sram write ac waveforms, ws controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21. sram write ac waveforms, e1s controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 22. sram write ac waveforms, ws controlled with gs low . . . . . . . . . . . . . . . . . . . 43 figure 23. sram write cycle waveform, ubs and lbs controlled, gs low . . . . . . . . . . . . . 43 table 23. sram write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 24. sram low v dds data retention ac waveforms, e1 s or ub s / lb s controlled . . 45 table 24. sram low v dds data retention characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 appendix a. block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25. top boot block addresses, m36w416tg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. bottom boot block addresses, m36w416bg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5/62 m36w416tg, m36w416bg appendix b. common flash interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 27. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 28. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 29. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 30. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 31. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 32. security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 appendix c. flowcharts and pseudo codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 25. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 26. double word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 27. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 54 figure 28. erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 29. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . 56 figure 30. locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 appendix d. command interface and program/erase controller state . . . . . . . 59 table 33. write state machine current/next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 34. write state machine current/next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 35. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
m36w416tg, m36w416bg 6/62 summary description the m36w416tg is a low voltage multiple memo- ry product which combines two memory devices; a 16 mbit boot block flash memory and a 4 mbit sram. recommended operating conditions do not allow both the flash memory and the sram memory to be active at the same time. the memory is offered in a stacked lfbga66 (12x8mm, 8 x 8 active ball, 0.8 mm pitch) package and is supplied with all the bits erased (set to 1). figure 2. logic diagram table 1. signal names ai07940 20 a0-a19 e f dq0-dq15 v ddf m36w416tg m36w416bg g f v ssf 16 w f rp f wp f v ddqf e1 s g s w s ub s lb s v sss v ppf v dds e2 s a0-a17 flash and sram address inputs a18-a19 address inputs for flash chip only dq0-dq15 data input/output v ddf flash power supply v ddqf flash power supply for i/o buffers v ppf flash optional supply voltage for fast program & erase v ssf flash ground v dds sram power supply v sss sram ground nc not connected internally flash control functions e f chip enable input g f output enable input w f write enable input rp f reset input wp f write protect input sram control functions e1 s , e2 s chip enable inputs g s output enable input w s write enable input ub s upper byte enable input lb s lower byte enable input
7/62 m36w416tg, m36w416bg figure 3. lfbga connections (top view through package) ai90254 a 6 5 4 3 2 1 #2 #1 e b f a12 a13 a11 nc nc nc e2s dq12 v sss a2 a3 a6 a7 a18 ef a0 a4 nc nc dq4 ws dq15 a9 a16 dq6 dq13 nc wf a8 a10 a5 nc v ssf a17 rpf a15 a14 nc nc v ddf e1s a1 nc nc gf v dds dq7 dq5 dq14 nc v ssf v ddqf #4 #3 8 7 c dq10 dq11 a19 wpf v ppf dq3 dq2 d dq8 dq9 gs lbs ubs dq1 dq0 g h
m36w416tg, m36w416bg 8/62 signal description see figure 2 logic diagram and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a17). addresses a0-a17 are common inputs for the flash and the sram components. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they con- trol the commands sent to the command interface of the internal state machine. the flash memory is accessed through the chip enable ( e f ) and write enable (w f ) signals, while the sram is accessed through two chip enable (es ) and write enable (w s ) signals. address inputs (a18-a19). addresses a18-a19 are inputs for the flash component only. the flash memory is accessed through the chip en- able ( e f ) and write enable (w f ) signals data inputs/outputs (dq0-dq15). the data i/ o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a write bus operation. flash chip enable ( e f ). the chip enable input activates the flash memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the standby level. flash output enable (g f ). the output enable controls the data outputs during the bus read op- eration of the flash memory. flash write enable ( w f ). the write enable con- trols the bus write operation of the flash memo- rys command interface. the data and address inputs are latched on the rising edge of chip en- able, e f , or write enable, w f , whichever occurs first. flash write protect (wp f ). write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the block cannot be changed. when write protect is at v ih , the lock-down is disabled and the block can be locked or unlocked. (refer to table 6, read protection register and protection register lock). flash reset (rp f ). the reset input provides a hardware reset of the flash memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. after reset all blocks are in the locked state. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters read array mode, but a negative transition of chip enable or a change of the address is re- quired to ensure valid data outputs. sram chip enable (e1 s , e2 s ). the chip en- able inputs activate the sram memory control logic, input buffers and decoders. e1 s at v ih or e2 s at v il deselects the memory and reduces the power consumption to the standby level. e1 s or e2 s can also be used to control writing to the sram memory array, while w s remains at v il. it is not allowed to set e f at v il and, e1 s at v il or e2 s at v il at the same time. sram write enable (w s ). the write enable in- put controls writing to the sram memory array. w s is active low. sram output enable (g s ). the output enable gates the outputs through the data buffers during a read operation of the sram memory. g s is ac- tive low. sram upper byte enable (ub s ). the upper byte enable enables the upper bytes for sram (dq8-dq15). ub s is active low. sram lower byte enable (lb s ). the lower byte enable enables the lower bytes for sram (dq0-dq7). lb s is active low. v ddf and v dds supply voltages. v ddf pro- vides the power supply to the internal core of the flash memory device. it is the main power supply for all operations (read, program and erase). v ddqf and v dds supply voltage (2.7v to 3.3v). v ddqf provides the power supply for the flash memory i/o pins and v dds provides the power supply for the sram control pins. this allows all outputs to be powered independently of the flash core power supply, v ddf . v ddqf can be tied to v dds. v ppf program supply voltage. v ppf is both a control input and a power supply pin for the flash memory. the two functions are selected by the voltage range applied to the pin. the supply volt- age v ddf and the program supply voltage v ppf can be applied in any order. if v ppf is kept in a low voltage range (0v to 3.6v) v ppf is seen as a control input. in this case a volt- age lower than v pplk gives an absolute protection against program or erase, while v ppf > v pp1 en- ables these functions (see table 6, dc character- istics for the relevant values). v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase op- erations continue. if v ppf is in the range 11.4v to 12.6v it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is com- pleted (see table 19 and 20).
9/62 m36w416tg, m36w416bg v ssf and v sss ground. v ssf and v sss are the ground reference for all voltage measurements in the flash and sram chips, respectively. note: each device in a system should have v d- df , v ddqf and v ppf decoupled with a 0.1f ca- pacitor close to the pin. see figure 9, ac measurement load circuit. the pcb trace widths should be sufficient to carry the re- quired v ppf program and erase currents. functional description the flash and sram components have separate power supplies and grounds and are distinguished by three chip enable inputs: e f for the flash mem- ory and e1 s and e2 s for the sram. recommended operating conditions do not allow both the flash and the sram to be in active mode at the same time. the most common example is simultaneous read operations on the flash and the sram which would result in a data bus con- tention. therefore it is recommended to put the sram in the high impedance state when reading the flash and vice versa (see table 2 main oper- ation modes for details). figure 4. functional block diagram ai07941 flash memory 16 mbit (x16) v ssf e f g f w f rp f wp f e1 s g s w s ub s lb s dq0-dq15 v ddf v ppf a18-a19 a0-a17 sram 4 mbit (x16) v sss v dds v ddqf e2 s
m36w416tg, m36w416bg 10/62 table 2. main operation modes note: x = dont care = v il or v ih , v ppfh = 12v 5%. operation mode e f g f w f rp f wp f v ppf e1 s e2 s g s w s ub s lb s dq7-dq0 dq15-dq8 flash memory read v il v il v ih v ih x dont care sram must be disabled data output write v il v ih v il v ih x v ddf or v ppfh sram must be disabled data input block locking v il xx v ih v il dont care sram must be disabled x standby v ih xx v ih x dont care any sram mode is allowed hi-z reset x x x v il x dont care any sram mode is allowed hi-z output disable v il v ih v ih v ih x dont care any sram mode is allowed hi-z sram read flash must be disabled v il v ih v il v ih v il v il data out word read flash must be disabled v il v ih v il v ih v ih v il data out hi-z flash must be disabled v il v ih v il v ih v il v ih hi-z data out write flash must be disabled v il v ih xv il v il v il data in word write flash must be disabled v il v ih xv il v ih v il data in hi-z flash must be disabled v il v ih xv il v il v ih hi-z data in standby/ power down any flash mode is allowable v ih v il x x x x hi-z xxxx v ih v ih hi-z data retention any flash mode is allowable v ih v il x x x x hi-z xxxx v ih v ih hi-z output disable any flash mode is allowable v il v ih v ih v ih v il v il hi-z any flash mode is allowable v il v ih v ih v ih v ih v il hi-z any flash mode is allowable v il v ih v ih v ih v il v ih hi-z
11/62 m36w416tg, m36w416bg maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 3. absolute maximum ratings note: 1. depends on range. symbol parameter value unit min max t a ambient operating temperature (1) C40 85 c t bias temperature under bias C40 125 c t stg storage temperature C55 150 c v io input or output voltage C0.5 v ddqf +0.3 v v ddf , v ddqf flash supply voltage C0.5 3.8 v v ppf program voltage C0.6 13 v v dds sram supply voltage C0.5 3.8 v
m36w416tg, m36w416bg 12/62 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 4, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 4. operating and ac measurement conditions figure 5. ac measurement i/o waveform note: v ddq means v ddqf = v dds figure 6. ac measurement load circuit table 5. device capacitance note: sampled only, not 100% tested. parameter sram flash memory units 70 70/85 min max min max v ddf supply voltage C C 2.7 3.3 v v ddqf = v dds supply voltage 2.7 3.3 2.7 3.3 v ambient operating temperature C 40 85 C 40 85 c load capacitance (c l ) 30 50 pf input rise and fall times 1v/ns 5ns input pulse voltages 0 to v ddqf 0 to v ddqf v input and output timing ref. voltages v ddqf /2 v ddqf /2 v ai90258 v ddq 0v v ddq /2 ai90259 v ddqf c l c l includes jig capacitance 25k device under test 0.1f v ddf 0.1f v ddqf 25k symbol parameter test condition typ max unit c in input capacitance v in = 0v, f=1 mhz 12 pf c out output capacitance v out = 0v, f=1 mhz 15 pf
13/62 m36w416tg, m36w416bg table 6. dc characteristics symbol parameter device test condition min typ max unit i li input leakage current flash & sram 0v v in v ddqf 1 a i lo output leakage current flash 0v v out v ddqf 10 a sram 0v v out v ddqf, sram outputs hi-z 1 a i dds v dd standby current flash e f = v ddqf 0.2v rp f = v ddq 0.2v 15 50 a sram e1 s v dds C 0.2v v in v dds C 0.2v or v in 0.2v f = fmax (a0-a17 and dq0- dq15 only) f = 0 (g s , w s , ub s and lb s ) 715a e1 s v dds C 0.2v v in v dds C 0.2v or v in 0.2v, f = 0 715a i ddd supply current (reset) flash rp f = v ssf 0.2v 15 50 a i dd supply current sram f = fmax = 1/ avav , v in 0.2v, i out = 0 ma 5.5 12 ma f = 1mhz, v in 0.2v, i out = 0 ma 1.5 3 ma i ddr supply current (read) flash e f = v il , g f = v ih, f = 5 mhz 10 20 ma i ddw supply current (program) flash program in progress v ppf = 12v 5% 10 20 ma program in progress v ppf = v ddf 10 20 ma i dde supply current (erase) flash erase in progress v ppf = 12v 5% 520ma erase in progress v ppf = v ddf 520ma i ddes supply current (program/erase suspend) flash e f = v ddqf 0.2v, erase suspended 50 a i pp1 program current (read or standby) flash v ppf > v ddf 400 a i pp2 program current (read or standby) flash v ppf v ddf 5a i ppr program current (reset) flash rp f = v ssf 0.2v 5a i ppw program current (program) flash v ppf = 12v 0.5v program in progress 10 ma v ppf = v ddf program in progress 5ma
m36w416tg, m36w416bg 14/62 i ppe program current (erase) flash v ppf = 12v 0.5v erase in progress 10 ma v ppf = v ddf erase in progress 5a v il input low voltage flash & sram v ddqf = v dds 2.7v C0.3 0.8 v v ih input high voltage flash & sram v ddqf = v dds 2.7v 0.7 v ddqf v ddqf +0.3 v v ol output low voltage flash & sram v ddqf = v dds = v dd min i ol = 100a 0.1 v v oh output high voltage flash & sram v ddqf = v dds = v dd min i oh = C100a v ddq C0.1 v v pp1 program voltage (program or erase operations) flash 1.65 3.6 v v ppfh program voltage (program or erase operations) flash 11.4 12.6 v v pplk program voltage (program and erase lock- out) flash 1 v v lko v ddf supply voltage (program and erase lock- out) flash 2 v symbol parameter device test condition min typ max unit
15/62 m36w416tg, m36w416bg package mechanical figure 7. stacked lfbga66-12x8mm, 8x8 ball array, 0.8mm pitch, bottom view package outline note: drawing is not to scale. table 7. stacked lfbga66 - 12x8mm, 8x8 ball array, 0.8 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.400 0.0551 a1 0.300 0.0118 a2 1.100 0.0433 b 0.400 0.300 0.500 0.0157 0.0118 0.0197 d 12.000 C C 0.4724 C C d1 5.600 C C 0.2205 C C d2 8.800 C C 0.3465 C C ddd 0.100 0.0039 e 8.000 C C 0.3150 C C e1 5.600 C C 0.2205 C C e 0.800 C C 0.0315 C C fd 1.600 C C 0.0630 C C fe 1.200 C C 0.0472 C C sd 0.400 C C 0.0157 C C se 0.400 C C 0.0157 C C a2 a1 a bga-z12 ddd d e e b se fd fe e1 e d1 sd d2 ball "a1"
m36w416tg, m36w416bg 16/62 figure 8. stacked lfbga66 daisy chain - package connections (top view through package) ai90273 d c #4 #3 8 7 6 1 e f a b h g 5 4 3 2 #1 #2
17/62 m36w416tg, m36w416bg figure 9. stacked lfbga66 daisy chain - pcb connections proposal (top view through package) #1 ai90274 d c e f a b h g start point end point #4 #3 8 7 6 15 4 3 2 #2
m36w416tg, m36w416bg 18/62 part numbering table 8. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. table 9. daisy chain ordering scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. example: m36w416 t g 70 za 6 t device type m36 = mmp (flash + sram) operating voltage w = v ddf = 2.7v to 3.3v, v dds = v ddqf = 2.7v to 3.3v sram chip size & organization 4 = 4 mbit (256kb x 16 bit) flash chip size & organization 16 = 16 mbit (x16), boot block array matrix t = top boot b = bottom boot sram component g = 4mb, 0.16m, 70ns, 3v speed 70 = 70ns 85 = 85ns package za = lfbga66: 12x8mm, 0.8mm pitch temperature range 1 = 0 to 70c 6 = C40 to 85c option t = tape & reel packing example: m36w416tg -za t device type m36w416tg daisy chain -za = lfbga66: 12x8mm, 0.8mm pitch option t = tape & reel packing
19/62 m36w416tg, m36w416bg flash device the m36w416tg contains one 16 mbit flash memory. this section describes how to use the flash device and all signals refer to the flash de- vice. flash summary description the flash memory is a 16 mbit (1 mbit x 16) non- volatile device that can be erased electrically at the block level and programmed in-system on a word-by-word basis. these operations can be performed using a single low voltage (2.7 to 3.6v) supply. v ddqf is used to drive the i/o pin down to 1.65v. an optional 12v v ppf power supply is pro- vided to speed up customer programming. the device features an asymmetrical blocked ar- chitecture with an array of 39 blocks: 8 parameter blocks of 4 kwords and 31 main blocks of 32 kwords. the m36w416tg has the parameter blocks at the top of the memory address space while the m36w416bg locates the parameter blocks starting from the bottom. the memory maps are shown in figure 10, block addresses. the flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any acciden- tal programming or erasure. there is an additional hardware protection against program and erase. when v ppf v pplk all blocks are protected against program or erase. all blocks are locked at power up. each block can be erased separately. erase can be suspended in order to perform either read or program in any other block and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles. the device includes a 128 bit protection register and a security block to increase the protection of a system design. the protection register is divid- ed into two 64 bit segments, the first one contains a unique device number written by st, while the second one is one-time-programmable by the us- er. the user programmable segment can be per- manently protected. the security block, parameter block 0, can be permanently protected by the user. figure 11, shows the flash security block memory map. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards.
m36w416tg, m36w416bg 20/62 figure 10. flash block addresses note: also see appendix a, tables 25 and 26 for a full listing of the flash block addresses. figure 11. flash security block and protection register memory map ai90256 4 kwords fffff ff000 32 kwords 0ffff 08000 32 kwords 07fff 00000 top boot block addresses 4 kwords f8fff f8000 32 kwords f0000 f7fff total of 8 4 kword blocks total of 31 32 kword blocks 4 kwords fffff f8000 32 kwords 32 kwords 00fff 00000 bottom boot block addresses 4 kwords f7fff 0ffff 32 kwords f0000 08000 total of 31 32 kword blocks total of 8 4 kword blocks 07fff 07000 ai07905 parameter block # 0 user programmable otp unique device number protection register lock 2 1 0 88h 85h 84h 81h 80h security block protection register
21/62 m36w416tg, m36w416bg flash bus operations there are six standard bus operations that control the device. these are bus read, bus write, out- put disable, standby, automatic standby and re- set. see table 2, main operation modes, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. read. read bus operations are used to output the contents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output en- able must be at v il in order to perform a read op- eration. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read de- pends on the previous command written to the memory (see command interface section). see figure 12, flash read mode ac waveforms, and table 18, flash read ac characteristics, for de- tails of when the output becomes valid. read mode is the default state of the device when exiting reset or after power-up. write. bus write operations write commands to the memory or latch input data to be programmed. a write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. see figures 13 and 14, flash write ac wave- forms, and tables 19 and 20, flash write ac characteristics, for details of the timing require- ments. output disable. the data outputs are high im- pedance when the output enable is at v ih . standby. standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in stand-by when chip enable is at v ih and the device is in read mode. the power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the de- vice enters standby mode when finished. automatic standby. automatic standby pro- vides a low power consumption state during read mode. following a read operation, the device en- ters automatic standby after 150ns of bus inactiv- ity even if chip enable is low, v il , and the supply current is reduced to i dd1 . the data inputs/out- puts will still output data if a bus read operation is in progress. reset. during reset mode when output enable is low, v il , the memory is deselected and the out- puts are high impedance. the memory is in reset mode when reset is at v il . the power consump- tion is reduced to the standby level, independently from the chip enable, output enable or write en- able inputs. if reset is pulled to v ss during a pro- gram or erase, this operation is aborted and the memory content is no longer valid.
m36w416tg, m36w416bg 22/62 flash command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. an internal program/erase controller han- dles all timings and verifies the correct execution of the program and erase commands. the pro- gram/erase controller provides a status register whose output may be read at any time during, to monitor the progress of the operation, or the pro- gram/erase states. see appendix 29, table 33, write state machine current/next, for a summary of the command interface. the command interface is reset to read mode when power is first applied, when exiting from re- set or whenever v dd is lower than v lko . com- mand sequences must be followed exactly. any invalid combination of commands will reset the de- vice to read mode. refer to table 10, com- mands, in conjunction with the text descriptions below. read memory array command the read command returns the memory to its read mode. one bus write cycle is required to is- sue the read memory array command and return the memory to read mode. subsequent read op- erations will read the addressed location and out- put the data. when a device reset occurs, the memory defaults to read mode. read status register command the status register indicates when a program or erase operation is complete and the success or failure of the operation itself. issue a read status register command to read the status registers contents. subsequent bus read operations read the status register at any address, until another command is issued. see table 17, status register bits, for details on the definitions of the bits. the read status register command may be is- sued at any time, even during a program/erase operation. any read attempt during a program/ erase operation will automatically output the con- tent of the status register. read electronic signature command the read electronic signature command reads the manufacturer and device codes and the block locking status, or the protection register. the read electronic signature command consists of one write cycle, a subsequent read will output the manufacturer code, the device code, the block lock and lock-down status, or the protec- tion and lock register. see tables 11, 12 and 13 for the valid address. read cfi query command the read query command is used to read data from the common flash interface (cfi) memory area, allowing programming equipment or appli- cations to automatically match their interface to the characteristics of the device. one bus write cycle is required to issue the read query com- mand. once the command is issued subsequent bus read operations read from the common flash interface memory area. see appendix b, common flash interface, tables 27, 28, 29, 30, 31 and 32 for details on the information contained in the common flash interface memory area. block erase command the block erase command can be used to erase a block. it sets all the bits within the selected block to 1. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write cycles are required to issue the command. the first bus cycle sets up the erase command. the second latches the block address in the internal state machine and starts the program/ erase controller. if the second bus cycle is not write erase confirm (d0h), status register bits b4 and b5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the block must be erased again. during erase operations the memory will accept the read status register command and the pro- gram/erase suspend command, all other com- mands will be ignored. typical erase times are given in table 14, program, erase times and pro- gram/erase endurance cycles. see appendix c, figure 28, erase flowchart and pseudo code, for a suggested flowchart for using the erase command. program command the memory array can be programmed word-by- word. two bus write cycles are required to issue the program command. the first bus cycle sets up the program command. the second latches the address and the data to be written and starts the program/erase controller. during program operations the memory will ac- cept the read status register command and the program/erase suspend command. typical pro- gram times are given in table 14, program, erase times and program/erase endurance cycles. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program
23/62 m36w416tg, m36w416bg operation is aborted, the block containing the memory location must be erased and repro- grammed. see appendix c, figure 25, program flowchart and pseudo code, for the flowchart for using the program command. double word program command this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.the two words must differ only for the address a0. programming should not be attempt- ed when v pp is not at v ppfh . the command can be executed if v pp is below v ppfh but the result is not guaranteed. three bus write cycles are necessary to issue the double word program command. the first bus cycle sets up the double word program command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. read operations output the status register con- tent after the programming has started. program- ming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. see appendix c, figure 26, double word pro- gram flowchart and pseudo code, for the flow- chart for using the double word program command. clear status register command the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register to 0. one bus write cycle is required to issue the clear status register command. the bits in the status register do not automatical- ly return to 0 when a new program or erase com- mand is issued. the error bits in the status register should be cleared before attempting a new program or erase command. program/erase suspend command the program/erase suspend command is used to pause a program or erase operation. one bus write cycle is required to issue the program/erase command and pause the program/erase control- ler. during program/erase suspend the command in- terface will accept the program/erase resume, read array, read status register, read electron- ic signature and read cfi query commands. ad- ditionally, if the suspend operation was erase then the program, block lock, block lock-down or protection program commands will also be ac- cepted. the block being erased may be protected by issuing the block protect, block lock or protec- tion program commands. when the program/ erase resume command is issued the operation will complete. only the blo cks not being erased may be read or programmed correctly. during a program/erase suspend, the device can be placed in a pseudo-standby mode by taking chip enable to v ih . program/erase is aborted if reset turns to v il . see appendix c, figure 27, program suspend & resume flowchart and pseudo code, and figure 29, erase suspend & resume flowchart and pseudo code for flowcharts for using the program/ erase suspend command. program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the command. once the command is issued subse- quent bus read operations read the status reg- ister. see appendix c, figure 27, program suspend & resume flowchart and pseudo code, and figure 29, erase suspend & resume flowchart and pseudo code for flowcharts for using the program/ erase resume command. protection register program command the protection register program command is used to program the 64 bit user one-time-pro- grammable (otp) segment of the protection reg- ister. the segment is programmed 16 bits at a time. when shipped all bits in the segment are set to 1. the user can only program the bits to 0. two write cycles are required to issue the protec- tion register program command. the first bus cycle sets up the protection register program command. the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the segment can be protected by programming bit 1 of the protection lock register. bit 1 of the pro- tection lock register protects bit 2 of the protec- tion lock register. programming bit 2 of the protection lock register will result in a permanent protection of the security block (see figure 11, flash security block and protection register memory map). attempting to program a previously protected protection register will result in a status register error. the protection of the protection
m36w416tg, m36w416bg 24/62 register and/or the security block is not revers- ible. the protection register program cannot be sus- pended. see appendix c, figure 31, protection register program flowchart and pseudo code, for the flowchart for using the protection register program command. block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked at power-up or reset. two bus write cycles are required to issue the block lock command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table. 16 shows the protection status after issuing a block lock command. the block lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. they are cleared by a blocks unlock command. refer to the section, block locking, for a detailed explanation. block unlock command the blocks unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to is- sue the blocks unlock command. the first bus cycle sets up the block unlock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table. 16 shows the protection status after issuing a block unlock command. refer to the section, block locking, for a detailed explanation. block lock-down command a locked block cannot be programmed or erased, or have its protection status changed when wp f is low, v il . when wp f is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock com- mand. two bus write cycles are required to issue the block lock-down command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. table. 16 shows the protection sta- tus after issuing a block lock-down command. refer to the section, block locking, for a detailed explanation.
25/62 m36w416tg, m36w416bg table 10. flash commands note: 1. x = dont care. 2. the signature addresses are listed in tables 11, 12 and 13. 3. addr 1 and addr 2 must be consecutive addresses differing only for a0. table 11. read electronic signature note: rp f = v ih . commands no. of cycles bus write operations 1st cycle 2nd cycle 3nd cycle bus op. addr data bus op. addr data bus op. addr data read memory array 1+ write x ffh read read addr data read status register 1+ write x 70h read x status register read electronic signature 1+ write x 90h read signature addr (2) signature read cfi query 1+ write x 98h read cfi addr query erase 2 write x 20h write block addr d0h program 2 write x 40h or 10h write addr data input double word program (3) 3 write x 30h write addr 1 data input write addr 2 data input clear status register 1 write x 50h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h block lock 2 write x 60h write block address 01h block unlock 2 write x 60h write block address d0h block lock-down 2 write x 60h write block address 2fh protection register program 2 write x c0h write address data input code device e f g f w f a0 a1 a2-a7 a8-a19 dq0-dq7 dq8-dq15 manufacture. code v il v il v ih v il v il 0 dont care 20h 00h device code m36w416tg v il v il v ih v ih v il 0 dont care ceh 88h m36w416bg v il v il v ih v ih v il 0 dont care cfh 88h
m36w416tg, m36w416bg 26/62 table 12. read block lock signature note: 1. a locked-down block can be locked "dq0 = 1" or unlocked "dq0 = 0"; see block locking section. table 13. read protection register and lock register table 14. program, erase times and program/erase endurance cycles block status e f g f w f a0 a1 a2-a7 a8-a11 a12-a19 dq0 dq1 dq2-dq15 locked block v il v il v ih v il v ih 0 dont care block address 1 0 00h unlocked block v il v il v ih v il v ih 0 dont care block address 0 0 00h locked-down block v il v il v ih v il v ih 0 dont care block address x (1) 1 00h word e f g f w f a0-a7 a8-a19 dq0 dq1 dq2 dq3-dq7 dq8-dq15 lock v il v il v ih 80h dont care 0 otp prot. data security prot. data 00h 00h unique id 0 v il v il v ih 81h dont care id data id data id data id data id data unique id 1 v il v il v ih 82h dont care id data id data id data id data id data unique id 2 v il v il v ih 83h dont care id data id data id data id data id data unique id 3 v il v il v ih 84h dont care id data id data id data id data id data otp 0 v il v il v ih 85h dont care otp data otp data otp data otp data otp data otp 1 v il v il v ih 86h dont care otp data otp data otp data otp data otp data otp 2 v il v il v ih 87h dont care otp data otp data otp data otp data otp data otp 3 v il v il v ih 88h dont care otp data otp data otp data otp data otp data parameter test conditions m36w416tg unit min typ max word program v pp = v dd 10 200 s double word program v pp = 12v 5% 10 200 s main block program v pp = 12v 5% 0.16 5 s v pp = v dd 0.32 5 s parameter block program v pp = 12v 5% 0.02 4 s v pp = v dd 0.04 4 s main block erase v pp = 12v 5% 110 s v pp = v dd 110 s parameter block erase v pp = 12v 5% 0.8 10 s v pp = v dd 0.8 10 s program/erase cycles (per block) 100,000 cycles
27/62 m36w416tg, m36w416bg flash block locking the flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. lock/unlock - this first level allows software- only control of block locking. lock-down - this second level requires hardware interaction before locking can be changed. v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the lock status of each block can be set to locked, unlocked, and lock-down. table 16, de- fines all of the possible protection states (wp f , dq1, dq0), and appendix c, figure 30, shows a flowchart for the locking operations. reading a blocks lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode write 90h to the device. subse- quent reads at the address specified in table 12, will output the lock status of that block. the lock status is represented by dq0 and dq1. dq0 indi- cates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when enter- ing lock-down. dq1 indicates the lock-down sta- tus and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. locked state the default status of all blocks on power-up or af- ter a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from any program or erase. any program or erase oper- ations attempted on a locked block will return an error in the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software com- mands. an unlocked block can be locked by issu- ing the lock command. unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be un- locked by issuing the unlock command. lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their lock status cannot be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked-down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the wp f input pin. when wp f =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from pro- gram, erase and protection status changes. when wp f =1 (v ih ) the lock-down function is disabled (1,1,1) and locked-down blocks can be individu- ally unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. these blocks can then be relocked (1,1,1) and unlocked (1,1,0) as desired while wp f remains high. when wp f is low , blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes made while wp f was high. device reset or power-down resets all blocks , including those in lock-down, to the locked state. locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase opera- tion, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the protection status will be changed. after completing any desired lock, read, or program op- erations, resume the erase operation with the erase resume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. refer to appendix d, com- mand interface and program/erase controller state, for detailed information on which com- mands are valid during erase suspend.
m36w416tg, m36w416bg 28/62 table 15. block lock status table 16. protection status note: 1. the protection status is defined by the write protect pin and by dq1 (1 for a locked-down block) and dq0 (1 for a lo cked block) as read in the read electronic signature command with a1 = v ih and a0 = v il . 2. all blocks are locked at power-up, so the default configuration is 001 or 101 according to wp f status. 3. a wp f transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. item address data block lock configuration xx002 lock block is unlocked dq0=0 block is locked dq0=1 block is locked-down dq1=1 current protection status (1) (wp f , dq1, dq0) next protection status (1) (wp f , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp f transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
29/62 m36w416tg, m36w416bg flash status register the status register provides information on the current or previous program or erase operation. the various bits convey information and errors on the operation. to read the status register the read status register command can be issued, re- fer to read status register command section. to output the contents, the status register is latched on the falling edge of the chip enable or output enable signals, and can be read until chip enable or output enable returns to v ih . either chip en- able or output enable must be toggled to update the latched data. bus read operations from any address always read the status register during program and erase operations. the bits in the status register are summarized in table 17, status register bits. refer to table 17 in conjunction with the following text descriptions. program/erase controller status (bit 7). the pro- gram/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is low (set to 0), the program/erase controller is active; when the bit is high (set to 1), the pro- gram/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high . during program, erase, operations the program/ erase controller status bit can be polled to find the end of the operation. other bits in the status reg- ister should not be tested until the program/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status, v pp status and block lock status bits should be tested for errors. erase suspend status (bit 6). the erase sus- pend status bit indicates that an erase operation has been suspended or is going to be suspended. when the erase suspend status bit is high (set to 1), a program/erase suspend command has been issued and the memory is waiting for a pro- gram/erase resume command. the erase suspend status should only be consid- ered valid when the program/erase controller sta- tus bit is high (program/erase controller inactive). bit 7 is set within 30s of the program/erase sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status (bit 5). the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. when the erase status bit is high (set to 1), the program/ erase controller has applied the maximum num- ber of pulses to the block and still failed to verify that the block has erased correctly. the erase sta- tus bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status (bit 4). the program status bit is used to identify a program failure. when the program status bit is high (set to 1), the pro- gram/erase controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. the program status bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. v pp status (bit 3). the v pp status bit can be used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can oc- cur if v pp becomes invalid during an operation. when the v pp status bit is low (set to 0), the volt- age on the v pp pin was sampled at a valid voltage; when the v pp status bit is high (set to 1), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and pro- gram and erase operations cannot be performed. once set high, the v pp status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program suspend status (bit 2). the program suspend status bit indicates that a program oper- ation has been suspended. when the program suspend status bit is high (set to 1), a program/ erase suspend command has been issued and the memory is waiting for a program/erase re- sume command. the program suspend status should only be considered valid when the pro-
m36w416tg, m36w416bg 30/62 gram/erase controller status bit is high (program/ erase controller inactive). bit 2 is set within 5s of the program/erase suspend command being is- sued therefore the memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status (bit 1). the block pro- tection status bit can be used to identify if a pro- gram or erase operation has tried to modify the contents of a locked block. when the block protection status bit is high (set to 1), a program or erase operation has been at- tempted on a locked block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new command is issued, otherwise the new command will appear to fail. reserved (bit 0). bit 0 of the status register is reserved. its value must be masked. note: refer to appendix c, flowcharts and pseudo codes, for using the status register. table 17. status register bits note: logic level 1 is high, 0 is low. bit name logic level definition 7 p/e.c. status 1 ready 0 busy 6 erase suspend status 1 suspended 0 in progress or completed 5 erase status 1 erase error 0 erase success 4 program status 1 program error 0 program success 3 v pp status 1 v pp invalid, abort 0 v pp ok 2 program suspend status 1 suspended 0 in progress or completed 1 block protection status 1 program/erase on protected block, abort 0 no operation to protected blocks 0 reserved
31/62 m36w416tg, m36w416bg figure 12. flash read mode ac waveforms table 18. flash read ac characteristics note: 1. sampled only, not 100% tested. 2. g f may be delayed by up to t elqv - t glqv after the falling edge of e f without increasing t elqv . symbol alt parameter flash unit 70 85 t avav t rc address valid to next address valid min 70 85 ns t av qv t acc address valid to output valid max 70 85 ns t axqx (1) t oh address transition to output transition min 0 0 ns t ehqx (1) t oh chip enable high to output transition min 0 0 ns t ehqz (1) t hz chip enable high to output hi-z max 20 20 ns t elqv (2) t ce chip enable low to output valid max 70 85 ns t elqx (1) t lz chip enable low to output transition min 0 0 ns t ghqx (1) t oh output enable high to output transition min 0 0 ns t ghqz (1) t df output enable high to output hi-z max 20 20 ns t glqv (2) t oe output enable low to output valid max 20 20 ns t glqx (1) t olz output enable low to output transition min 0 0 ns dq0-dq15 ai07906 a0-a19 e f g f valid taxqx tavav valid tavqv telqv telqx tglqv tglqx addr. valid chip enable outputs enabled data valid standby tghqx tghqz tehqx tehqz
m36w416tg, m36w416bg 32/62 figure 13. flash write ac waveforms, write enable controlled e f g f w f dq0-dq15 v ppf a0-a19 ai07907 wp f command cmd or data status register valid tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv twphwh twhgl tqvwpl twhel
33/62 m36w416tg, m36w416bg table 19. flash write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. 2. applicable if v ppf is seen as a logic input (v ppf < 3.6v). symbol alt parameter flash unit 70 85 t avav t wc write cycle time min 70 85 ns t avw h t as address valid to write enable high min 45 45 ns t dvwh t ds data valid to write enable high min 45 45 ns t elwl t cs chip enable low to write enable low min 0 0 ns t elqv chip enable low to output valid min 70 85 ns t qvvpl (1,2) output valid to v ppf low min 0 0 ns t qvwpl output valid to write protect low min 0 0 ns t vphwh (1) t vps v ppf high to write enable high min 200 200 ns t whax t ah write enable high to address transition min 0 0 ns t whdx t dh write enable high to data transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whel write enable high to output enable low min 25 25 ns t whgl write enable high to output enable low min 20 20 ns t whwl t wph write enable high to write enable low min 25 25 ns t wlwh t wp write enable low to write enable high min 45 45 ns t wphwh write protect high to write enable high min 45 45 ns
m36w416tg, m36w416bg 34/62 figure 14. flash write ac waveforms, chip enable controlled e f g f dq0-dq15 v ppf a0-a19 ai07908 w f wp f command cmd or data status register valid tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh power-up and set-up command confirm command or data input status register read 1st polling telqv twpheh tehgl tqvwpl
35/62 m36w416tg, m36w416bg table 20. flash write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. 2. applicable if v ppf is seen as a logic input (v ppf < 3.6v). symbol alt parameter flash unit 70 85 t avav t wc write cycle time min 70 85 ns t av eh t as address valid to chip enable high min 45 45 ns t dveh t ds data valid to chip enable high min 45 45 ns t ehax t ah chip enable high to address transition min 0 0 ns t ehdx t dh chip enable high to data transition min 0 0 ns t ehel t cph chip enable high to chip enable low min 25 25 ns t ehgl chip enable high to output enable low min 25 25 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t eleh t cp chip enable low to chip enable high min 45 45 ns t elqv chip enable low to output valid min 70 85 ns t qvvpl (1,2) output valid to v ppf low min 0 0 ns t qvwpl data valid to write protect low min 0 0 ns t vpheh (1) t vps v ppf high to chip enable high min 200 200 ns t wlel t cs write enable low to chip enable low min 0 0 ns t wpheh write protect high to chip enable high min 45 45 ns
m36w416tg, m36w416bg 36/62 figure 15. flash power-up and reset ac waveforms table 21. flash power-up and reset ac characteristics note: 1. the device reset is possible but not guaranteed if t plph < 100ns. 2. sampled only, not 100% tested. 3. it is important to assert rp f in order to allow proper cpu initialization during power up or reset. symbol parameter test condition flash unit 70 85 t phwl t phel t phgl reset high to write enable low, chip enable low, output enable low during program and erase min 50 50 s others min 30 30 ns t plph (1,2) reset low to reset high min 100 100 ns t vdhph (3) supply voltages high to reset high min 50 50 s ai07909b w f , rp f tphwl tphel tphgl e f , g f v ddf , v ddqf tvdhph tphwl tphel tphgl tplph power-up reset
37/62 m36w416tg, m36w416bg sram device this section describes how to use the sram and all signals refer to it. sram summary description the sram is a 4 mbit asynchronous random ac- cess memory which features super low voltage op- eration and low current consumption with an access time of 70 ns under all conditions. the memory operations can be performed using a sin- gle low voltage supply, 2.7v to 3.3v, which is the same as the flash components voltage supply. figure 16. sram logic diagram data in drivers 256kb x 16 ram array 2048 x 2048 column decoder row decoder a0-a10 w s ub s lb s sense amps a11-a17 power-down circuit dq0-dq7 dq8-dq15 g s ub s lb s ai 07939 e1 s e2 s
m36w416tg, m36w416bg 38/62 sram operations there are five standard operations that control the sram component. these are bus read, bus write, standby/power-down, data retention and output disable. a summary is shown in table 2, main operation modes read. read operations are used to output the contents of the sram array. the sram is in read mode whenever write enable, w s , is at v ih , out- put enable, g s , is at v il , chip enable, e1 s , is at v il , chip enable, e2 s , is at v ih , and one or both of the byte enable inputs, ub s and lb s is/are at v il . valid data will be available on the output pins after a time of t avqv after the last stable address. if the chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t e1lqv , t e2hqv , or t glqv ) rath- er than the address. data out may be indetermi- nate at t e1lqx , t e2hqx and t glqx , but data lines will always be valid at t avqv (see table 22, figures 17 and 18). write. write operations are used to write data to the sram. the sram is in write mode whenever w s and e1 s are at v il , and e2 s is at v ih . either the chip enable inputs, e1 s and e2 s , or the write enable input, w s , must be deasserted during ad- dress transitions for subsequent write cycles. a write operation is initiated when e1 s is at v il , e2 s is at v ih and w s is at v il . the data is latched on the falling edge of e1 s , the rising edge of e2 s or the falling edge of w s , whichever occurs last. the write cycle is terminated on the rising edge of e1 s , the rising edge of w s or the falling edge of e2 s , whichever occurs first. if the output is enabled (e1 s =v il , e2 s =v ih and g s =v il ), then w s will return the outputs to high im- pedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of op- eration. the data input must be valid for t dvwh be- fore the rising edge of write enable, for t dve1h before the rising edge of e1 s or for t dve2l before the falling edge of e2 s , whichever occurs first, and remain valid for t whdx , t e1hax or t e2lax (see table 23, figures 20, 21, 22 and 23). standby/power-down. the sram component has a chip enabled power-down feature which in- vokes an automatic standby mode (see table 22, figure 19). the sram is in standby mode when- ever either chip enable is deasserted, e1 s at v ih or e2 s at v il . it is also possible when ub s and lb s are at v ih . data retention. the sram data retention per- formance as v dds goes down to v dr are de- scribed in table 24 and figure 24. in e1 s controlled data retention mode, the minimum standby current mode is entered when e1 s v dds C 0.2v and e2 s 0.2v or e2 s v dds C 0.2v. in e2 s controlled data reten- tion mode, minimum standby current mode is en- tered when e2 s 0.2v. output disable. the data outputs are high im- pedance when the output enable, g s , is at v ih with write enable, w s , at v ih .
39/62 m36w416tg, m36w416bg figure 17. sram read mode ac waveforms, address controlled with ub s = lb s = v il note: e1 s = low, e2 s = high, g s = low, w s = high. figure 18. sram read ac waveforms, g s controlled note: write enable (w s ) = high. address valid prior to or at the same time as e1 s , ub s and lb s going low. figure 19. sram standby ac waveforms ai07942 tavav tavqv taxqx a0-a17 dq0-dq15 valid data valid data valid ai07943 tavav te1lqv te1hqz tglqv tglqx tghqz data valid a0-a17 e1 s g s dq0-dq15 te2hqv valid te2lqz e2 s tblqv tblqx tbhqz ub s , lb s te1lqx te2hqx ai07913 tpd e2 s i dd tpu 50% e1 s
m36w416tg, m36w416bg 40/62 table 22. sram read ac characteristics note: 1. sampled only. not 100% tested. symbol alt parameter sram unit min max t avav t rc read cycle time 70 ns t av qv t acc address valid to output valid 70 ns t axqx t oh address transition to output transition 10 ns t bhqz t bhz ub s , lb s disable to hi-z output 25 ns t blqv t ab ub s , lb s access time 70 ns t blqx t blz ub s , lb s enable to low-z output 5ns t e1lqv t e2hqv t acs1 chip enable 1 low or chip enable 2 high to output valid 70 ns t e1lqx t e2hqx t clz1 chip enable 1 low or chip enable 2 high to output transition 10 ns t e1hqz t e2lqz t hzce chip enable high or chip enable 2 low to output hi-z 25 ns t ghqz t ohz output enable high to output hi-z 25 ns t glqv t oe output enable low to output valid 35 ns t glqx t olz output enable low to output transition 5 ns t pd (1) chip enable 1 high or chip enable 2 low to power down 70 ns t pu (1) chip enable 1 low or chip enable 2 high to power up 0 ns
41/62 m36w416tg, m36w416bg figure 20. sram write ac waveforms, w s controlled note: w s , e1 s , e2 s , ub s and/or lb s must be asserted to initiate a write cycle. output enable (g s ) = low (otherwise, dq0-dq15 are high impedance). if e1 s , e2 s and w s are deasserted at the same time, dq0-dq15 remain high impedance. 2. the i/o pins are in output mode and input signals must not be applied. ai07944 tavav twhax tdvwh input valid a0-a17 e1 s w s dq0-dq15 valid e2 s tavwh tblwh tghqz twhdz tavwl ub s , lb s te2hwh te1lwh g s twlwh note 2
m36w416tg, m36w416bg 42/62 figure 21. sram write ac waveforms, e1 s controlled note: 1. w s , e1 s , e2 s , ub s and/or lb s must be asserted to initiate a write cycle. output enable (g s ) = low (otherwise, dq0-dq15 are high impedance). if e1 s , e2 s and w s are deasserted at the same time, dq0-dq15 remain high impedance. 2. if e1 s , e2 s and w s are deasserted at the same time, dq0-dq15 remain high impedance. 3. the i/o pins are in output mode and input signals must not be applied. ai07945 tavav te1hax tdve1h tdve2l input valid a0-a17 e1 s w s dq0-dq15 valid e2 s tave1h tave2l tble1h tble2l tghqz te1hdz te2ldz tave1l ub s , lb s te2he2l te1le1h g s twle1h twle2l tave2h te2lax note 3
43/62 m36w416tg, m36w416bg figure 22. sram write ac waveforms, w s controlled with g s low note: 1. if e1 s , e2 s and w s are deasserted at the same time, dq0-dq15 remain high impedance. figure 23. sram write cycle waveform, ub s and lb s controlled, g s low note: 1. if e1 s , e2 s and w s are deasserted at the same time, dq0-dq15 remain high impedance. ai07946 tavav twhax tdvwh input valid a0-a17 e1 s w s dq0-dq15 valid e2 s tavwh twlwh tavwl twhdz twhqx tblwh ub s , lb s te1lwh te2hwh twlqz ai07947 tavav tbhax tdvbh input valid a0-a17 e1 s w s dq0-dq15 valid e2 s tavbh twlbh tavbl tbhdz tblbh ub s , lb s te1lbh te2hbh
m36w416tg, m36w416bg 44/62 table 23. sram write ac characteristics symbol alt parameter sram unit min max t avav t wc write cycle time 70 ns t av e1l , t ave 2h , t avwl, t avbl t as address valid to beginning of write 0 ns t ave 1h , t ave2l t aw address valid to chip enable 1 low or chip enable 2 high 60 ns t av wh t aw address valid to write enable high 60 ns t blwh t ble1h t ble2l t av bh t bw ub s , lb s valid to end of write 60 ns t blbh t bw ub s , lb s low to ub s , lb s high 60 ns t dve1h , t dve2l , t dvwh t dvbh t dw input valid to end of write 30 ns t e1hax , t e2lax , t whax t bhax t wr end of write to address change 0 ns t e1hdz , t e2ldz , t whdz t bhdz t hd address transition to end of write 0 ns t e1le1h , t e1lbh t e1lwh t cw1 chip enable 1 low to end of write 60 ns t e2he2l, t e2hbh, t e2hwh t cw2 chip enable 2 high to end of write 60 ns t ghqz t ghz output enable high to output hi-z 25 ns t whqx t dh write enable high to input transition 5 ns t wlbh t wp write enable low to ub s , lb s high 50 ns t wlqz t whz write enable low to output hi-z 25 ns t wlwh t wle1h t wle2l t wp write enable pulse width 50 ns
45/62 m36w416tg, m36w416bg figure 24. sram low v dds data retention ac waveforms, e1 s or ub s / lb s controlled table 24. sram low v dds data retention characteristic note: 1. all other inputs v ih v dds C0.2v or v il 0.2v. 2. sampled only. not 100% tested. symbol parameter test condition min typ max unit i dddr supply current (data retention) v dds = 1.5v, e1 s v dds C 0.2v, v in v dds C 0.2v or v in 0.2v 310a v dr supply voltage (data retention) 1.5 3.3 v t cdr chip disable to power down 0 ns t r operation recovery time 70 ns ai07918 e1 s or ub s , lb s tcdr v dds tr data retention mode v dds (min) v dds (min)
m36w416tg, m36w416bg 46/62 appendix a. block address tables table 25. top boot block addresses, m36w416tg table 26. bottom boot block addresses, m36w416bg # size (kword) address range 0 4 ff000-fffff 1 4 fe000-fefff 2 4 fd000-fdfff 3 4 fc000-fcfff 4 4 fb000-fbfff 5 4 fa000-fafff 6 4 f9000-f9fff 7 4 f8000-f8fff 8 32 f0000-f7fff 99 32 e8000-effff 10 32 e0000-e7fff 11 32 d8000-dffff 12 32 d0000-d7fff 13 32 c8000-cffff 14 32 c0000-c7fff 15 32 b8000-bffff 16 32 b0000-b7fff 17 32 a8000-affff 18 32 a0000-a7fff 19 32 98000-9ffff 20 32 90000-97fff 21 32 88000-8ffff 22 32 80000-87fff 23 32 78000-7ffff 24 32 70000-77fff 25 32 68000-6ffff 26 32 60000-67fff 27 32 58000-5ffff 28 32 50000-57fff 29 32 48000-4ffff 30 32 40000-47fff 31 32 38000-3ffff 32 32 30000-37fff 33 32 28000-2ffff 34 32 20000-27fff 35 32 18000-1ffff 36 32 10000-17fff 37 32 08000-0ffff 38 32 00000-07fff # size (kword) address range 38 32 f8000-fffff 37 32 f0000-f7fff 36 32 e8000-effff 35 32 e0000-e7fff 34 32 d8000-dffff 33 32 d0000-d7fff 32 32 c8000-cffff 31 32 c0000-c7fff 30 32 b8000-bffff 29 32 b0000-b7fff 28 32 a8000-affff 27 32 a0000-a7fff 26 32 98000-9ffff 25 32 90000-97fff 24 32 88000-8ffff 23 32 80000-87fff 22 32 78000-7ffff 21 32 70000-77fff 20 32 68000-6ffff 19 32 60000-67fff 18 32 58000-5ffff 17 32 50000-57fff 16 32 48000-4ffff 15 32 40000-47fff 14 32 38000-3ffff 13 32 30000-37fff 12 32 28000-2ffff 11 32 20000-27fff 10 32 18000-1ffff 9 32 10000-17fff 8 32 08000-0ffff 7 4 07000-07fff 6 4 06000-06fff 5 4 05000-05fff 4 4 04000-04fff 3 4 03000-03fff 2 4 02000-02fff 1 4 01000-01fff 0 4 00000-00fff
47/62 m36w416tg, m36w416bg appendix b. common flash interface (cfi) the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. tables 27, 28, 29, 30, 31 and 32 show the addresses used to re- trieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see table 32, security code area). this area can be accessed only in read mode by the final user. it is impossible to change the security num- ber after it has been written by st. issue a read command to return to read mode. table 27. query structure overview note: query data are always presented on the lowest order data outputs. table 28. cfi query identification string note: query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are 0. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description value 00h 0020h manufacturer code st 01h 88ceh 88cfh device code to p bottom 02h-0fh reserved reserved 10h 0051h "q" 11h 0052h query unique ascii string "qry" "r" 12h 0059h "y" 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm intel compatible 14h 0000h 15h 0035h address for primary algorithm extended query table (see table 30) p = 35h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (0000h means none exists) na 18h 0000h 19h 0000h address for alternate algorithm extended query table (0000h means none exists) na 1ah 0000h
m36w416tg, m36w416bg 48/62 table 29. cfi query system interface information offset data description value 1bh 0027h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 2.7v 1ch 0036h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 3.6v 1dh 00b4h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.4v 1eh 00c6h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.6v 1fh 0004h typical time-out per single word program = 2 n s 16s 20h 0004h typical time-out for double word program = 2 n s 16s 21h 000ah typical time-out per individual block erase = 2 n ms 1s 22h 0000h typical time-out for full chip erase = 2 n ms na 23h 0005h maximum time-out for word program = 2 n times typical 512s 24h 0005h maximum time-out for double word program = 2 n times typical 512s 25h 0003h maximum time-out per individual block erase = 2 n times typical 8s 26h 0000h maximum time-out for chip erase = 2 n times typical na
49/62 m36w416tg, m36w416bg table 30. device geometry definition offset word mode data description value 27h 0015h device size = 2 n in number of bytes 2 mbyte 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0002h 0000h maximum number of bytes in multi-byte program or page = 2 n 4 2ch 0002h number of erase block regions within the device. it specifies the number of regions within the device containing contiguous erase blocks of the same size. 2 m36w416tg 2dh 2eh 001eh 0000h region 1 information number of identical-size erase block = 001eh+1 31 2fh 30h 0000h 0001h region 1 information block size in region 1 = 0100h * 256 byte 64 kbyte 31h 32h 0007h 0000h region 2 information number of identical-size erase block = 0007h+1 8 33h 34h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8 kbyte m36w416bg 2dh 2eh 0007h 0000h region 1 information number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8 kbyte 31h 32h 001eh 0000h region 2 information number of identical-size erase block = 001eh+1 31 33h 34h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64 kbyte
m36w416tg, m36w416bg 50/62 table 31. primary algorithm-specific extended query table note: 1. see table 28, offset 15 for p pointer definition. offset p = 35h (1) data description value (p+0)h = 35h 0050h primary algorithm extended query table unique ascii string pri "p" (p+1)h = 36h 0052h "r" (p+2)h = 37h 0049h "i" (p+3)h = 38h 0031h major version number, ascii "1" (p+4)h = 39h 0030h minor version number, ascii "0" (p+5)h = 3ah 0066h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported (1 = yes, 0 = no) bit 1 suspend erase supported (1 = yes, 0 = no) bit 2 suspend program supported (1 = yes, 0 = no) bit 3 legacy lock/unlock supported (1 = yes, 0 = no) bit 4 queued erase supported (1 = yes, 0 = no) bit 5 instant individual block locking supported (1 = yes, 0 = no) bit 6 protection bits supported (1 = yes, 0 = no) bit 7 page mode read supported (1 = yes, 0 = no) bit 8 synchronous read supported (1 = yes, 0 = no) bit 31 to 9 reserved; undefined bits are 0 no ye s ye s no no ye s ye s no no (p+6)h = 3bh 0000h (p+7)h = 3ch 0000h (p+8)h = 3dh 0000h (p+9)h = 3eh 0001h supported functions after suspend read array, read status register and cfi query are always supported during erase or program operation bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are 0 yes (p+a)h = 3fh 0003h block lock status defines which bits in the block status register section of the query are implemented. address (p+a)h contains less significant byte bit 0 block lock status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are 0 ye s ye s (p+b)h = 40h 0000h (p+c)h = 41h 0030h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 3v (p+d)h = 42h 00c0h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12v (p+e)h = 43h 0001h number of protection register fields in jedec id space. "00h," indicates that 256 protection bytes are available 01 (p+f)h = 44h 0080h protection field 1: protection description this field describes user-available. one time programmable (otp) protection register bytes. some are pre-programmed with device unique serial numbers. others are user programmable. bits 0C15 point to the protection register lock byte, the sections first byte. the following bytes are factory pre-programmed and user-programmable. bit 0 to 7 lock/bytes jedec-plane physical low address bit 8 to 15 lock/bytes jedec-plane physical high address bit 16 to 23 "n" such that 2 n = factory pre-programmed bytes bit 24 to 31 "n" such that 2 n = user programmable bytes 80h (p+10)h = 45h 0000h 00h (p+11)h = 46h 0003h 8 byte (p+12)h = 47h 0003h 8 byte (p+13)h = 48h reserved
51/62 m36w416tg, m36w416bg table 32. security code area offset data description 80h 00xx protection register lock 81h xxxx 64 bits: unique device number 82h xxxx 83h xxxx 84h xxxx 85h xxxx 64 bits: user programmable otp 86h xxxx 87h xxxx 88h xxxx
m36w416tg, m36w416bg 52/62 appendix c. flowcharts and pseudo codes figure 25. program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v ppf invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write 40h or 10h ai07919 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v ppf invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (any_address, 0x40) ; /*or writetoflash (any_address, 0x10) ; */ do { status_register=readflash (any_address) ; /* e f or g f must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*v ppf invalid error */ error_handler ( ) ; yes end yes no b1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
53/62 m36w416tg, m36w416bg figure 26. double word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v ppf invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 and address 2 must be consecutive addresses differing only for bit a0. write 30h ai07920 start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v ppf invalid error (1, 2) program error (1, 2) yes end yes no b1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) double_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2) { writetoflash (any_address, 0x30) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (any_address) ; /* e f or g f must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*v ppf invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
m36w416tg, m36w416bg 54/62 figure 27. program suspend & resume flowchart and pseudo code write 70h ai07921 read status register yes no b7 = 1 yes no b2 = 1 program continues write d0h read data from another address start write b0h program complete write ffh read data program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (any_address) ; /* e f or g f must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b2==0) /*program completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ } } write ffh
55/62 m36w416tg, m36w416bg figure 28. erase flowchart and pseudo code note: if an error is found, the status register must be cleared before further program/erase operations. write 20h ai07922 start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 yes b4, b5 = 1 v ppf invalid error (1) command sequence error (1) no no b5 = 0 erase error (1) end yes no b1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (any_address, 0x20) ; writetoflash (blocktoerase, 0xd0) ; /* only a12-a20 are significannt */ /* memory enters read status state after the erase command */ } while (status_register.b7== 0) ; do { status_register=readflash (any_address) ; /* e f or g f must be toggled*/ if (status_register.b3==1) /*v ppf invalid error */ error_handler ( ) ; if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ; }
m36w416tg, m36w416bg 56/62 figure 29. erase suspend & resume flowchart and pseudo code write 70h ai07923 read status register yes no b7 = 1 yes no b6 = 1 erase continues write d0h read data from another block or program/protection program or block protect/unprotect/lock start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (any_address) ; /* e f or g f must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b6==0) /*erase completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume erase*/ } }
57/62 m36w416tg, m36w416bg figure 30. locking operations flowchart and pseudo code write 01h, d0h or 2fh ai04364 read block lock states yes no locking change confirmed? start write 60h locking_operation_command (address, lock_operation) { writetoflash (any_address, 0x60) ; /*configuration setup*/ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (any_address, 0xff) ; /*reset to read array mode*/ } write ffh write 90h end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (any_address, 0x90) ;
m36w416tg, m36w416bg 58/62 figure 31. protection register program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v ppf invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write c0h ai07924 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v ppf invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (any_address, 0xc0) ; do { status_register=readflash (any_address) ; /* e f or g f must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*v ppf invalid error */ error_handler ( ) ; yes end yes no b1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
59/62 m36w416tg, m36w416bg appendix d. command interface and program/erase controller state table 33. write state machine current/next, sheet 1 of 2. note: cmd = command, elect.sg. = electronic signature, ers = erase, prog. = program, prot = protection, sus = suspend. current state sr bit 7 data when read command input (and next state) read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ers resume (d0h) read status (70h) clear status (50h) read array 1 array read array prog.setup ers. setup read array read sts. read array read status 1 status read array program setup erase setup read array read status read array read elect.sg. 1 electronic signature read array program setup erase setup read array read status read array read cfi query 1 cfi read array program setup erase setup read array read status read array lock setup 1 status lock command error lock (complete) lock cmd error lock (complete) lock command error lock cmd error 1 status read array program setup erase setup read array read status read array lock (complete) 1 status read array program setup erase setup read array read status read array prot. prog. setup 1 status protection register program prot. prog. (continue) 0 status protection register program continue prot. prog. (complete) 1 status read array program setup erase setup read array read status read array prog. setup 1 status program program (continue) 0 status program (continue) prog. sus read sts program (continue) prog. sus status 1 status prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array prog. sus read array 1 array prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array prog. sus read elect.sg. 1 electronic signature prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array prog. sus read cfi 1 cfi prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array program (complete) 1 status read array program setup erase setup read array read status read array erase setup 1 status erase command error erase (continue) erase cmderror erase (continue) erase command error erase cmd.error 1 status read array program setup erase setup read array read status read array erase (continue) 0 status erase (continue) erase sus read sts erase (continue) erase sus read sts 1 status erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase sus read array 1 array erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase sus read elect.sg. 1 electronic signature erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase sus read cfi 1 cfi erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase (complete) 1 status read array program setup erase setup read array read status read array
m36w416tg, m36w416bg 60/62 table 34. write state machine current/next, sheet 2 of 2. note: cmd = command, elect.sg. = electronic signature, prog. = program, prot = protection. current state command input (and next state) read elect.sg. (90h) read cfi query (98h) lock setup (60h) prot. prog. setup (c0h) lock confirm (01h) lock down confirm (2fh) unlock confirm (d0h) read array read elect.sg. read cfi query lock setup prot. prog. setup read array read status read elect.sg. read cfi query lock setup prot. prog. setup read array read elect.sg. read elect.sg. read cfi query lock setup prot. prog. setup read array read cfi query read elect.sg. read cfi query lock setup prot. prog. setup read array lock setup lock command error lock (complete) lock cmd error read elect.sg. read cfi query lock setup prot. prog. setup read array lock (complete) read elect.sg. read cfi query lock setup prot. prog. setup read array prot. prog. setup protection register program prot. prog. (continue) protection register program (continue) prot. prog. (complete) read elect.sg. read cfi query lock setup prot. prog. setup read array prog. setup program program (continue) program (continue) prog. suspend read status prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) prog. suspend read array prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) prog. suspend read elect.sg. prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) prog. suspend read cfi prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) program (complete) read elect.sg. read cfiquery lock setup prot. prog. setup read array erase setup erase command error erase (continue) erase cmd.error read elect.sg. read cfi query lock setup prot. prog. setup read array erase (continue) erase (continue) erase suspend read status erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase suspend read array erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase suspend read elect.sg. erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase suspend read cfi query erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase (complete) read elect.sg. read cfi query lock setup prot. prog. setup read array
61/62 m36w416tg, m36w416bg revision history table 35. document revision history date version revision details 19-nov-2002 1.0 first issue
m36w416tg, m36w416bg 62/62 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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